1. Field of the Invention
The present invention relates to debouncing an input signal such as from a switch, particularly a mechanical switch, or some other monitored signal, which may suffer transient voltage variations.
2. Description of the Related Art
When a mechanical switch is opened or closed, a mechanical contact is physically moved from one position to another. This momentum can prevent a clean opening or closing of the switch. In particular, when the switch is closing, the moving contact of a switch may move rapidly towards the other contact. As the two contacts come together, the electrical circuit is completed and the switch is “electrically” closed. However the momentum of the switch may cause the moving contact to deflect off the other contact or “bounce”. As the moving contact deflects away from the other contact, the electrical circuit is broken again. The biasing of the switch will eventually bring the moving contact back towards the other contact, again making electrical connection. However, the moving contact may again bounce, again breaking the electrical contact. This may be repeated a number of times until the mechanical energy of the contact has been dissipated and the two contacts remain physically and hence electrically connected, until the switch is activated again.
FIG. 1 shows a simple circuit that may be used to obtain an input from a mechanical switch. The switch 1 is connected to a biasing resistor 2. The biasing resistor holds the output at the supply voltage until the switch closes. As the switch closes, the bouncing of the contact causes the output of the circuit to repeatedly switch between the two supply rails until the bouncing of the switch ceases.
Depending upon how the output of mechanical switches is utilised, the bouncing effect may appear as multiple actuations of the switch. For example, if the switch is a simple push to activate type switch, it may appear as though the user has activated the switch several times when in fact they have simply operated the switch once.
To overcome this problem circuits, known as debounce circuits, have been used to mitigate the effects of switch bounce. These circuits typically involve taking the input from the switch and delaying it for a predetermined period of time. If the switch continues to stay in the same state for the duration of the delay, the circuit provides an output indicating the new state of the switch only after the predetermined amount of time.
For example, U.S. Pat. No. 4,523,104 describes an arrangement which passes the output of a switch into a shift register. The signal is serially shifted through a series of stages of the shift register. The output from each of the stages of the shift register is passed into a NAND gate. In this way, only if the input from the switch remains in the same state for the time it takes for an input to pass through the shift register will the output state change. Any brief transition back to the off state will reset the output. The transient will have to pass entirely through the register before the output can go back to a high output.
Other methods of achieving debounce include using a counter. The counter is started when the switch is closed and the input signal changes state. If the input reverts to its original state due to bounce, the counter is reset. When the input signal changes state again, the counting begins again. Thus the counter only reaches a predefined value after the input has remained in the same state for a sufficient duration, namely the debounce time. Only after this value is reached does the output change state.
FIG. 2 shows a circuit which also provides a debounce function with a synchroniser on the output. A series of D-type flip-flops 20, 21 are used to synchronise the input and to provide the debounce function. A clock labelled SLOW_CLK is used to provide the clock signal to the flip-flops. The input signal (DATA) from the switch is provided to a first flip-flop 20. As the switch is actuated the input DATA goes high. At the next clock transition, the flip-flop 20a output Q0 switches to high. This is in turn fed to the next flip-flop 20b which in turn has its output Q1 switched to high at the next clock transition. The function of the flip-flops 20a, 20b is to synchronise the input signal to the SLOW_CLK signal. Two flip-flops are provided to avoid metastability problems.
Metastability problems occur where the data input changes state at roughly the same time as the clock changes state. This can lead to the output of the flip-flop becoming metastable, i.e. an undefined voltage which is neither of the valid digital logic states. If this output was used directly on the downstream logic elements, this could lead to unpredictable outputs. This can also lead to high currents. Consequently, to avoid metastability problems, a second flip-flop 20b is used. This helps to prevent a metastable output from the first flip-flop from propagating to the downstream logic components.
The probability of a flip-flop becoming metastable is fairly low. However, the problems caused by metastability mean that it is now customary to use multistage flip-flops for synchronization of an asynchronous input to a synchronous system. The drawback of this is that the synchroniser introduces additional delay before the output switches changes state in response to a change of state of the input.
Referring again to FIG. 2, the output Q1 is then passed through the two flip-flops 21a, 21b, each of which delay the input signal by one clock cycle. FIG. 3 shows the typical signals passing through the circuit of FIG. 2. In this example, the flip-flops switch on the positive going cycle of the clock signal SLOW_CLK. The switch is actuated and, at time t0, first makes an electrical contact. At time t1, the first subsequent clock transition takes place and the first flip-flop 20a switches to provide a high output.
At time t2, the bounce of the switch reopens the electrical circuit whereupon the input again falls to a low level. However, as the switch remakes the electrical contact before the next clock transition, this transition is not detected by the flip-flop 20a. Consequently, at the next clock transition, with the input again high, the output Q0 of flip-flop 20a, remains high. Simultaneously, the previously high input to flip-flop 20b means that the output Q1 of flip-flop 20b now also becomes high. At time t3, the switch again bounces open. Even though the switch remains electrically disconnected for almost one clock cycle, because the period does not coincide with a clock transition, it is again undetected by the first flip-flop 20a. Consequently, at the next clock transition, the output Q0 remains high. Output Q1 remains high and output Q2 from flip-flop 21a now becomes high. At the next clock transition, the input is still high and the sequence of high signals passes through the flip-flops such that the output Q3 from flip-flop 21b becomes high.
The outputs Q1, Q2 and Q3 are fed to an AND gate 22 which provides the output from the debounce circuit. As the output Q3 switches to high, all the inputs to the AND gate are now high and the output of the circuit, DEB_OUT, switches to high. The output will remain high until such a time as the input signal DATA is at a low level during a clock transition. At time t4, the input signal DATA switches to low and remains low through the next clock transition. Consequently, the output from flip-flop Q0 switches to low. At the next clock cycle, the low input is fed into input flip-flop 20b and output Q1 goes low. This causes the output of the circuit from AND gate 22 to also switch to low. This low value will then pass through the flip-flops 21a and 21b keeping the output low until the input has been high for at least three (3-4) clock cycles.
The circuit of FIG. 2 can provide a debounce function principally by delaying the time before the output changes state, to ensure that any bouncing of the switch contacts is completed before the circuit output switches. In the example of FIG. 2, the output DEB_OUT does not go high until two clock cycles after the output of the synchroniser Q1 goes high. This represents at least three clock cycles from the closure of the switch. However, it will be apparent that transitions of the input which take place between transitions of the clock may not be detected so unless sufficient debounce time is provided, undetected switch bounce may still be occurring when the output switches to high. If a bounce is then detected, this will result in the output switch switching back to low again. In effect these circuits simply provide a delay of sufficient length after an initial change in the input to reasonably ensure that bouncing has ended. Consequently, these circuits can either be unreliable, if the delay is too short, or alternatively have to be designed to have sufficiently long delays to ensure that any bounce is completed before the output switches state.
The problem of detecting short duration transitions or glitches of the input signal can be reduced by increasing the clock speed. However, to avoid reducing the safety margin, this requires more delay stages, i.e. the flip-flops 21a, 21b, in order to maintain the overall debounce time. For example, it may be required to have a debounce time of 2 seconds. In the circuit shown in FIG. 2 a 1 Hz clock would be required to provide this. This means that glitches of less than 1 second may be undetected by the circuit. If the clock speed was increased to 1 kHz, then only glitches of less than 1 ms would remain undetected. However, it would be necessary to have a much larger shift register or counter. A shift register with 2,000 delay stages or an 11 bit counter would be needed to provide the same 2 s debounce time. This makes the debounce circuitry extremely complex, requiring a large number of components and needing a significant amount of power. These types of debounce circuits are often needed on portable electronic equipment where large size and power usage are unacceptable.
It is therefore desirable to provide a debounce circuit which is capable of providing a sufficiently long debounce period to accommodate the worst case settling time for mechanical switches but which is also able to detect short glitches caused by bouncing of the switch contacts to prevent the output from switching to the on state before bouncing has stopped.
The need for this type of debouncing of an input signal also occurs where signals such as power supply voltage levels are being monitored to make sure they meet predetermined criteria. In the case of the voltage of a power source, it might be desirable to make sure the voltage exceeds a certain level to ensure proper operation of a powered device. If the level drops below the threshold, switching to an alternate source can be carried out to avoid interruption to the operation of the device. During normal operation, the voltage level may drop (or rise) transiently such as due to surges in demand on the supply. Such short transients do not warrant switching to an alternate supply as the supply will normally recover in a short time.
It is therefore desirable to avoid sensitivity to such limited duration transients. This can be provided by a debounce circuit similar to that used for monitoring switches with appropriate adjustment according to the time scales involved. However, similar problems with prior art systems described above also apply. There is therefore a need for a debounce circuit which can overcome or alleviate the problems with the prior art to provide a debounce function for switches or monitored voltage levels.
Preferably, such a debounce bounce circuit will be able to delay switching its output after an input changes state and remains in that state without reverting to its previous state for a minimum debounce period. The debounce circuit is preferably able to detect reversions to the previous state even if they are for a period shorter than the debounce period. It may further be desirable to provide the ability to provide the debounce delay function when the input transitions from a first state to a second state as well as when it reverts from the second state back to the first state.